Electrochemical deposition (ECD) is an important technique in the manufacture of semiconductor devices and components, hard disk drive fabrication, and other applications. With the recent growth of interest in 3D integration of wafers, there is a developing interest in providing conductive layers in through silicon vias (TSVs). One of the most promising candidates for depositing conductors in features greater than 1 micron in diameter and less than 10:1 aspect ratio is electrochemical deposition of copper. Because of the relatively large feature sizes associated with this type of implementation scheme in comparison with conventional interconnects in logic or memory devices, long cycle times in the deposition tools are required. For productivity reasons, it is desirable to reduce the cycle times of the process equipment and to make the tools as efficient as possible.
In electrochemical deposition of copper (ECD Cu) in semiconductor applications, a wafer is placed in an electrolyte (typically an aqueous solution of CuSO4/H2SO4 plus small quantities of organic additives) and a DC potential (or pulsed DC) is applied between an immersed Cu electrode (anode) and a continuous Cu seed layer (cathode) on the wafer being coated. The inverse of this approach—electropolishing—can also be carried out to remove Cu from the surface of a wafer by making the wafer surface the anode and the corresponding electrode the cathode.
Due to the high value of semiconductor wafers it is desirable to ensure that as much as possible of the wafer surface is used. To achieve this aim for deposition or electropolishing processes a highly uniform coating is required to cover the wafer surface as close as possible to the edge of the wafer. The area at the edge of the wafer which is not intended to be used is commonly known as the region of edge exclusion. This is defined as a band “x” mm from the edge of the wafer. The size of the edge exclusion zone is wafer size and process dependent.
Automated ECD systems typically use a handling robot to move wafers from the load/unload station from cassettes/FOUPS to a pre-clean station followed by one or more ECD deposition stations and ultimately a post deposition clean station before returning to the cassette/FOUP. In conventional ECD stations the wafer is immersed in the electrolyte and electrical contact to the wafer surface is achieved by contacts to the wafer edge. A fluid seal also made to the wafer surface and typically this seal protect the wafer contacts from contact with electrolyte. Two generic approaches are typically used—horizontal (wafer face to be coated facing down) “Fountain cells” and vertical “Rack” systems.
Fountain cell systems, where the electrolyte is sprayed vertically at a wafer rotating face down in a plating bath, retain the wafer in a clamshell type fixture which provides a fluid seal and electrical contact to the wafer surface. U.S. Pat. Nos. 6,156,167 and 7,118,658 disclose systems of this type. The clamshell is loaded and unloaded at the ECD cell, typically automatically with a wafer transport robot. This load/unload cycle occurs outside the electrolyte. Once the fixture is loaded it is then immersed into a tank of electrolyte which contains the submerged anode assembly.
In vertical rack type systems such as disclosed in U.S. Pat. Nos. 8,029,653 and 7,445,697, another variant of a clamshell type fixture is used. This fixture is not required to rotate however one fixture must move from one process station to the next before it is finally opened prior to leaving the tool. While this reduces the number of times the edge seal/contact must be made it does complicate the pre and post deposition steps.
An alternative approach to ECD has been suggested by U.S. Pat. Nos. 6,077,412, 5,853,559 and WO 2012/080716, where the wafer is placed horizontal parallel with the anode as in “Fountain cell” arrangement but this time the surface to be coated is facing up. The challenge with this type of arrangement is to minimize the loss of electrolyte from the system as when the cell is opened and quantity of electrolyte flows over the edge of the wafer. The lost electrolyte adds to cost (as it must be replaced) but also acts as a source of contamination for subsequent process steps.
Whilst a conventional clamshell type enclosure could be used in the type of arrangement there are significant costs associated with such an approach—not least the need for automated closure/opening of the clamshell and a further requirement for a seal between the clamshell and the electrolyte cavity. What is needed is a cost effective closure and fluid removal mechanism. Desirably, such a mechanism would enable the low volume cavity cell described in WO 2012/080716 to be realized without the complications and additional costs associated with prior art approaches.
For a low volume cavity ECD cell to operate productively the amount of fluid entering and leaving the system must be minimized while a reliable fluid seal and electrical contact is made to the wafer surface very close (preferably within about 2 mm) to the edge of the wafer. Care must be also taken to ensure bubbles or trapped pockets of air/N2/gas can readily leave the cell as these can have a detrimental effect on film uniformity.
Fluid transport into/from the cell can be achieved by a pressure gradient eg. a gas purge or a pump. However one of the key challenges for this type of low volume cell is to provide a means of removing the electrolyte from the cell in such a fashion that no electrolyte flows beyond the edge of front surface of the wafer when the cell is opened. This is desirable as when electrolyte progresses beyond the edge of the wafer it will contaminate the backside of the wafer, the platen top and any transport mechanism that comes in contact with the electrolyte.
In the clamshell approaches adopted in fountain cells and rack based cells a containment fixture which seals the wafer edge, provides electrical contact and is used to transport the wafer to/from the bath of electrolyte. Electrolyte can be removed from the wafer surface with the fluid seal in place outside the plating cell.
In U.S. Pat. No. 6,077,412, the disclosed system is designed for the wafer to be cleaned in situ within the plating chamber by means of deionised water rinse and spin dry. In this case a relatively large volume chamber is used to contain the electrolyte, and fluid removal is achieved by lowering the wafer support plate. Fluid will be removed from the system rapidly; however the fluid will flow over the edge of the wafer. This necessitates an in situ clean and a large vessel outside the plating cell providing the secondary containment region. Whilst fluid removal may be aided for recycling purposes by small pipes, these will not be sufficient to avoid the in situ clean and the secondary containment region as relatively large amounts of fluid will remain on the wafer surface when the chamber is opened.
In U.S. Pat. No. 5,853,559, it is suggested to use a small tube close to the surface of the wafer to reduce the amount of electrolyte left on the wafer surface (and increase the amount re-cycled) prior to a deionised water rinse of the remaining fluid.
Both U.S. Pat. Nos. 6,077,412 and 5,853,559 disclose systems where the volume of the chambers is large, i.e., the wafer to anode separation is equal to or greater than the wafer width. Also, the present inventors have realised that the use of tubes and pipes is undesirable, because they can interfere with dielectric properties of the chamber and they can impose restrictions on fluid removal rates.